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1 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance ? ? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. double data rate (ddr) sdram mt46v128m4 ? 32 meg x 4 x 4 banks mt46v64m8 ? 16 meg x 8 x 4 banks mt46v32m16 ? 8 meg x 16 x 4 banks for the latest data sheet revisions, please refer to the micron web site: www.micron.com/datasheets pin assignment (top view) 66-pin tsop features ?v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v bidirectional data strobe (dqs) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two ? one per byte) internal, pipelined double-data-rate (ddr) architecture; two data accesses per clock cycle differential clock inputs (ck and ck#) commands entered on each positive ck edge dqs edge-aligned with data for reads; center- aligned with data for writes dll to align dq and dqs transitions with ck four internal banks for concurrent operation data mask (dm) for masking write data (x16 has two ? one per byte) programmable burst lengths: 2, 4, or 8 x16 has programmable iol/iov. concurrent auto precharge option is supported auto refresh and self refresh modes longer lead tsop for improved reliability (ocpl) 2.5v i/o (sstl_2 compatible) options marking configuration 128 meg x 4 (32 meg x 4 x 4 banks) 128m4 64 meg x 8 (16 meg x 8 x 4 banks) 64m8 32 meg x 16 (8 meg x 16 x 4 banks) 32m16 plastic package ? ocpl 66-pin tsop (standard 22.3mm length) tg (400 mil width, 0.65mm pin pitch) timing ? cycle time 7.5ns @ cl = 2 (ddr266b) 1 -75z 7.5ns @ cl = 2.5 (ddr266b) 2 -75 10ns @ cl = 2 (ddr200) 2 -8 self refresh standard none low power l note: 1. supports pc2100 modules with 2-3-3 timing 2. supports pc2100 modules with 2.5-3-3 timing 3. supports pc1600 modules with 2-2-2 timing 128 meg x 4 64 meg x 8 32 meg x 16 configuration 32 meg x 4 x 4 banks 16 meg x 8 x 4 banks 8 meg x 16 x 4 banks refresh count 8k 8k 8k row addressing 8k (a0?a12) 8k (a0?a12) 8k (a0?a12) bank addressing 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) column addressing 4k (a0?a9, a 11, a12) 2k (a0?a9, a11) 1k (a0?a9) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ss q udqs dnu v ref v ss udm ck# ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss x16 v dd dq0 v dd q dq1 dq2 vssq dq3 dq4 v dd q dq5 dq6 vssq dq7 nc v dd q ldqs nc v dd dnu ldm we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd x16 v ss dq7 v ss q nc dq6 v dd q nc dq5 v ss q nc dq4 v dd q nc nc v ss q dqs dnu v ref v ss dm ck# ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss x8 x4 v ss nc v ss q nc dq3 v dd q nc nc v ss q nc dq2 v dd q nc nc v ss q dqs dnu v ref v ss dm ck# ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss v dd dq0 v dd q nc dq1 v ss q nc dq2 v dd q nc dq3 v ss q nc nc v dd q nc nc v dd dnu nc we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd x8 x4 v dd nc v dd q nc dq0 v ss q nc nc v dd q nc dq1 v ss q nc nc v dd q nc nc v dd dnu nc we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd key timing parameters speed clock rate data-out access dqs-dq grade cl = 2** cl = 2.5** window* window skew -75 133 mhz 133 mhz 2.5ns 0.75ns +0.5ns -75 100 mhz 133 mhz 2.5ns 0.75ns +0.5ns -8 100 mhz 125 mhz 3.4ns 0.8ns +0.6ns *minimum clock rate @ cl = 2 (-8) and cl = 2.5 (-75) **cl = cas (read) latency
2 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance general description the 512mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. it is internally configured as a quad- bank dram. the 512mb ddr sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n - prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512mb ddr sdram effectively consists of a single 2 n -bit wide, one-clock- cycle data transfer at the internal dram core and two corresponding n -bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted ex- ternally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 offering has two data strobes, one for the lower byte and one for the upper byte. the 512mb ddr sdram operates from a differen- tial clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then followed by a read or write command. the address bits regis- tered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write com- mand are used to select the bank and the starting col- umn location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self- timed row precharge that is initiated at the end of the burst access. as with standard sdr sdrams, the pipelined, multibank architecture of ddr sdrams allows for con- current operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power-saving power-down mode. all inputs are com- patible with the jedec standard for sstl_2. all full drive strength outputs are sstl_2, class ii compat- ible. note: 1. the functionality and the timing specifications discussed in this data sheet are for the dll-enabled mode of operation. 2. throughout the data sheet, the various figures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq collectively, unless specifically stated otherwise. additionally, the x16 is divided in to two bytes?the lower byte and upper byte. for the lower byte (dq0 through dq7) dm refers to ldm and dqs refers to ldqs; and for the upper byte (dq8 through dq15) dm refers to udm and dqs refers to udqs. (note: xx= -75, -75z, or -8) 512mb ddr sdram part numbers part number configuration i/o drive level ref resh option mt46v128m4tg-xx 128 meg x 4 full drive standard mt46v128m4tg-xxl 128 meg x 4 full drive low power mt46v64m8tg-xx 64 meg x 8 full drive standard mt46v64m8tg-xxl 64 meg x 8 full drive low power mt46v32m16tg-xx 32 meg x 16 programmable drive standard mt46v32m16tg-xxl 32 meg x 16 programmable drive low power
3 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance table of contents functional block diagram ? 128 meg x 4 ............. 4 functional block diagram ? 64 meg x 8 ............... 5 functional block diagram ? 32 meg x 16 ............. 6 pin descriptions ...................................................... 7 functional description ......................................... 9 initialization ...................................................... 9 register definition ............................................. 9 mode register ............................................... 9 burst length ............................................ 9 burst type ................................................ 10 read latency ........................................... 11 operating mode ...................................... 11 extended mode register ............................... 12 dll enable/disable ................................. 12 commands ............................................................ 13 truth table 1 (commands) ....................................... 13 truth table 1a (dm operation) ................................. 13 deselect .............................................................. 14 no operation (nop) .......................................... 14 load mode register ........................................... 14 active ................................................................ 14 read ................................................................ 14 write ................................................................ 14 precharge ........................................................... 14 auto precharge .................................................. 14 burst terminate ................................................. 14 auto refresh ...................................................... 15 self refresh ......................................................... 15 operation .............................................................. 16 bank/row activation ....................................... 16 reads ................................................................ 17 read burst .................................................... 18 consecutive read bursts .............................. 19 nonconsecutive read bursts ....................... 20 random read accesses ................................ 21 terminating a read burst ............................ 23 read to write ............................................... 24 read to precharge ......................................... 25 writes ................................................................ 26 write burst .................................................... 27 consecutive write to write ......................... 28 nonconsecutive write to write .................. 29 random writes ............................................ 30 write to read ? uninterrupting .................. 31 write to read ? interrupting ....................... 32 write to read ? odd, interrupting ............. 33 write to precharge ? uninterrupting .......... 34 write to precharge ? interrupting ............... 35 write to precharge ? odd, interrupting ...... 36 precharge ........................................................... 37 power-down ..................................................... 37 truth table 2 (cke) ................................................. 38 truth table 3 (current state, same bank) ..................... 39 truth table 4 (current state, different bank) ................. 41 operating conditions absolute maximum ratings .................................... 43 dc electrical and operating conditions ..................... 43 ac input operating conditions ........................... 43 clock input operating conditions ....................... 44 capacitance ? x4, x8 .............................................. 45 i dd specifications and conditions ? x4, x8 ........... 45 capacitance ? x16 .................................................. 46 i dd specifications and conditions ? x16 ............... 46 ac electrical characteristics (timing table) .......... 47 slew rate derating table ....................................... 48 data valid window derating ............................... 52 voltage and timing waveforms nominal output drive curves ......................... 53 reduced output drive curves (x16 only) ........ 54 output timing ? t dqsq and t qh - x4, x8 ...... 55 output timing ? t dqsq and t qh - x16 .......... 56 output timing ? t ac and t dqsck ................. 57 input timing ..................................................... 57 input voltage .................................................... 58 initialize and load mode registers .................. 59 power-down mode .......................................... 60 auto refresh mode ........................................... 61 self refresh mode ............................................. 62 reads bank read - without auto precharge ........ 63 bank read - with auto precharge .............. 64 writes bank write ? without auto precharge ....... 65 bank write ? with auto precharge ............. 66 write ? dm operation ................................ 67 66-pin tsop (tg) dimensions ............................... 68
4 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance functional block diagram 128 meg x 4 13 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch mode registers 12 command decode a0-a12, ba0, ba1 cke 13 address register 15 2048 (x8) 16,384 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 2,048 x 8) bank0 row- address latch & decoder 8192 sense amplifiers bank control logic 13 bank1 bank2 bank3 13 11 1 2 2 refresh counter 4 4 4 1 input registers 1 1 1 1 rcvrs 1 8 8 2 8 ck out data dqs mask data ck ck col0 col0 ck in drvrs dll mux dqs generator 4 4 4 4 4 8 dq0 - dq3, dm dqs 1 read latch write fifo & drivers
5 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance functional block diagram 64 meg x 8 13 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch mode registers 11 command decode a0-a12, ba0, ba1 cke 13 address register 15 1024 (x16) i/o gating dm mask logic column decoder bank0 memory array (8192 x 1024 x 16) bank0 row- address latch & decoder 8192 bank control logic 13 bank1 bank2 bank3 13 10 2 2 refresh counter 8 8 8 1 input registers 1 1 1 1 rcvrs 1 16 16 2 16 ck out data dqs mask data ck ck ck in drvrs dll mux dqs generator 8 8 8 8 8 16 dq0 - dq7, dm dqs 1 read latch write fifo & drivers 1 col0 col0 16,384 sense amplifiers
6 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance functional block diagram 32 meg x 16 13 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch mode registers 10 command decode a0-a12, ba0, ba1 cke 13 address register 15 512 (x32) i/o gating dm mask logic column decoder bank0 memory array (8,192 x 512 x 32) bank0 row- address latch & decoder 8192 bank control logic 13 bank1 bank2 bank3 13 9 2 2 refresh counter 16 16 16 2 input registers 2 2 2 2 rcvrs 2 32 32 4 32 ck out data dqs mask data ck ck ck in drvrs dll mux dqs generator 16 16 16 16 16 32 dq0 - dq15, ldm, udm ldqs udqs 2 read latch write fifo & drivers 1 col0 col0 16,384 sense amplifiers
7 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance pin descriptions tsop pin numbers symbol type description 45, 46 ck, ck# input cl ock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs) is referenced to the crossings of ck and ck#. 44 cke input clock enab le: cke high activates and cke low deactivates the internal clock, input buffers and output drivers. taking cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit and for disabling the outputs. cke must be maintained high throughout read and write accesses. input buffers (excluding ck, ck# and cke) are disabled during power- down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_2 input but will detect an lvcmos low level after v dd is applied. 24 cs# input chip select: cs# enables (registered low) and disables (regis- tered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. 23, 22, 21 ras#, cas#, i nput comm and inputs: ras#, cas#, and we# (along with cs#) define the we# command being entered. 47 dm input input data mask: dm is an input mask signal for write data. input 20, 47 ldm, udm data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins. for the x16 , ldm is dm for dq0- dq7 and udm is dm for dq8-dq15. pin 20 is a nc on x4 and x8 26, 27 ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. 29-32, 35-40, a0 ? a12 input address inputs: provide the row address for active commands, and 28, 41, 42 the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by ba0, ba1) or all banks (a10 high). the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode register) is loaded during the load mode register command. 2, 4, 5, 7, 8, 10, 11, 13, dq0 ? 15 i/o data input/output: data bus for x16 (4, 7, 10, 13, 54, 57, 60, and 63 54, 56, 57, 59, 60, 62, are nc for x8), (2, 4, 7, 8,10, 13, 54, 57, 59, 60, 63, and 65 for x4). 63, 65 (continued on next page)
8 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance pin descriptions (continued) tsop pin numbers symbol type description reserved nc pins 1 tsop pin numbers symbol type description 17 a13 i address input for 1gb devices. note: 1. nc pins not listed may also be reserved for other uses now or in the future. this table simply defines specific nc pins deemed to be of importance. 2, 5, 8, 11, 56, 59, 62, 65 dq0-7 i/o data input/output: data bus for x8 (2, 8, 59 and 65 are nc for x4). 5, 11, 56, 62 dq0-3 i/o data input/output: data bus for x4. 51 dqs i/o data strobe: output with read data, input with write data. dqs is 16, 51 ldqs, udqs edge-aligned with read data, centered in write data. it is used to capture data. for the x16 , ldqs is dqs for dq0-dq7 and udqs is dqs for dq8-dq15. pin 16 is nc on x4 and x8. 50 dnu ? do not use: must float to minimize noise. 3, 9, 15, 55, 61 v dd q supply dq p ower supply: +2.5v 0.2v. isolated on the die for improved noise immunity. 6, 12, 52, 58, 64 v ss q supply dq ground. isolated on the die for improved noise immunity. 1, 18, 33 v dd supply power supply: +2.5v 0.2v. 34, 48, 66 v ss supply ground. 49 v ref supply sstl_2 reference voltage. 14, 17, 19, 25, 43, 53 nc ? no connect: these pins should be left unconnected.
9 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance functional description the 512mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. the 512mb ddr sdram is internally configured as a quad-bank dram. the 512mb ddr sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n - prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512mb ddr sdram consists of a single 2 n -bit wide, one-clock-cycle data transfer at the internal dram core and two correspond- ing n -bit wide, one-half-clock-cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then followed by a read or write command. the address bits regis- tered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a12 select the row). the address bits registered coincident with the read or write com- mand are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram must be initialized. the following sections provide detailed in- formation covering device initialization, register defi- nition, command descriptions and device operation. initialization ddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. power must first be applied to v dd and v dd q simul- taneously, and then to v ref (and to the system v tt ). v tt must be applied after v dd q to avoid device latch-up, which may cause permanent damage to the device. v ref can be applied any time after v dd q but is expected to be nominally coincident with v tt . except for cke, inputs are not recognized as valid until after v ref is applied. cke is an sstl_2 input but will detect an lvcmos low level after v dd is applied. maintaining an lvcmos low level on cke during power-up is re- quired to ensure that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal operation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200s delay prior to applying an executable command. once the 200s delay has been satisfied, a dese- lect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a load mode register command should be issued for the extended mode register (ba1 low and ba0 high) to enable the dll, followed by another load mode register command to the mode register (ba0/ ba1 both low) to reset the dll and to program the operating parameters. two-hundred clock cycles are required between the dll reset and any read com- mand. a precharge all command should then be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed ( t rfc must be satisfied.) addition- ally, a load mode register command for the mode register with the reset dll bit deactivated (i.e., to pro- gram operating parameters without resetting the dll) is required. following these requirements, the ddr sdram is ready for normal operation. register definition mode register the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency and an operating mode, as shown in fig- ure 1. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is pro- grammed again or the device loses power (except for bit a8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed cor- rectly. the mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified opera- tion. mode register bits a0-a2 specify the burst length, a3 specifies the type of burst (sequential or inter- leaved), a4-a6 specify the cas latency, and a7-a12 specify the operating mode. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being program- mable, as shown in figure 1. the burst length deter- mines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both
10 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 1 mode register definition the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively se- lected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely se- lected by a1-a i when the burst length is set to two, by a2-a i when the burst length is set to four and by a3-a i when the burst length is set to eight (where a i is the most significant column address bit for a given con- table 1 burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 note: 1. for a burst length of two, a1-a i select the two- data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-a i select the four- data-element block; a0-a1 select the first access within the block. 3. for a burst length of eight, a3-a i select the eight- data-element block; a0-a2 select the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. figuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 1. m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - 0 0 - valid valid - 0 1 burst type sequential interleaved cas latency reserved reserved 2 reserved reserved reserved 2.5 reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 * m14 and m13 (ba0 and ba1) must be ? 0, 0 ? to select the base mode register (vs. the extended mode register). m9 m10 m12 m11
11 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance table 2 cas latency (cl) read latency the read latency is the delay, in clock cycles, be- tween the registration of a read command and the availability of the first bit of output data. the latency can be set to 2, or 2.5 clocks, as shown in figure 2. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . table 2 indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 2 cas latency operating mode the normal operating mode is selected by issuing a mode register set command with bits a7-a12 each set to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9-a12 each set to zero, bit a8 set to one, and bits a0-a6 set to the desired values. although not required by the micron device, jedec specifications recommend when a load mode register command is issued to reset the dll, it should always be followed by a load mode regis- ter command to select normal operating mode. all other combinations of values for a7-a12 are re- served for future use and/or test modes. test modes and reserved states should not be used because un- known operation or incompatibility with future ver- sions may result. ck ck# command dq dqs cl = 2 read nop nop nop read nop nop nop burst length = 4 in the cases shown shown with nominal t ac and nominal t dsdq ck ck# command dq dqs cl = 2.5 t0 t1 t2 t2n t3 t3n t0 t1 t2 t2n t3 t3n don ? t care transitioning data allowable operating frequency (mhz) speed cl = 2 cl = 2.5 -75z 75 f 133 75 f 133 -75 75 f 100 75 f 133 -8 75 f 100 75 f 125
12 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 3 extended mode register definition extended mode register the extended mode register controls functions be- yond those controlled by the mode register; these ad- ditional functions are dll enable/disable and output drive strength. these functions are controlled via the bits shown in figure 3. the extended mode register is programmed via the load mode regis- ter command to the mode register (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. the en- abling of the dll should always be followed by a load mode register command to the mode register (ba0/ ba1 both low) to reset the dll. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiat- ing any subsequent operation. violating either of these requirements could result in unspecified operation. output drive strength the normal drive strength for all outputs are speci- fied to be sstl2, class ii. the x16 supports an option for reduced drive. this option is intended for the sup- port of the lighter load and/or point-to-point environ- ments. the selection of the reduced drive strength will alter the dqs and dqss from sstl2, class ii drive strength to a reduced drive strength, which is approxi- mately 54% of the sstl2, class ii drive strength. the micron (32meg x16) device supports a programmable drive strength option. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll for the purpose of debug or evalua- tion. (when the device exits self refresh mode, the dll is enabled automatically.) any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. operating mode reserved reserved 0 ? 0 ? valid ? 0 1 dll enable disable dll 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 654 3 8 2 1 0 e0 0 1 drive strength normal reduced e1 2 0 ? qfc# function disabled reserved e2 3 e0 e1, operating mode a10 a11 a12 ba1 ba0 10 11 12 13 14 note: 1. e14 and e13 (ba0 and ba1) must be ? 1, 0 ? to select the extended mode register (vs. the base mode register). 2. the reduced drive strength option is not supported on the x4 and x8 versions, and is only available on the x16 version. 3. the qfc# option is not supported. e2, e3 e4 0 ? 0 ? 0 ? 0 ? 0 ? e6 e5 e7 e8 e9 0 ? 0 ? e10 e11 0 ? e12 ds qfc#
13 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance appear following the operation section; these tables provide current state/next state information. commands truth table 1 provides a quick reference of avail- able commands. this is followed by a verbal descrip- tion of each command. two additional truth tables note: 1. cke is high for all commands shown except self refresh. 2. ba0-ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 select extended mode register; other combinations of ba0-ba1 are reserved). a0-a12 provide the op- code to be written to the selected mode register. 3. ba0-ba1 provide bank address and a0-a12 provide row address. 4. ba0-ba1 provide bank address; a0-a i provide column address (where i = 9 for x16, 9,11 for x8, and 9, 11, 12 for x4); a10 high enables the auto precharge feature (nonpersistent), and a10 low disables the auto precharge feature. 5. a10 low: ba0-ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0-ba1 are ? don ? t care. ? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ? don ? t care ? except for cke. 8. applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 9. deselect and nop are functionally interchangeable. 10. used to mask write data; provided coincident with the corresponding data. truth table 1 ? commands (note: 1) name (function) cs# ras# cas# we# addr notes deselect (nop) h x x x x 9 no operation (nop) l h h h x 9 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) l h l h bank/col 4 write (select bank and column, and start write burst) l h l l bank/col 4 burst terminate l h h l x 8 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh l l l h x 6, 7 (enter self refresh mode) load mode register l l l l op-code 2 truth table 1a ? dm operation (note: 10) name (function) dm dqs notes write enable l valid write inhibit hx
14 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance deselect the deselect function (cs# high) prevents new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected ddr sdram to perform a nop (cs# low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode registers are loaded via inputs a0?a12. see mode register descriptions in the register defini- tion section. the load mode register command can only be issued when all banks are idle, and a subse- quent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a12 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before open- ing a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a i (where i = 9 for x16; 9, 11 for x8; or 9, 11, and 12 for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a i (where i = 9 for x16; 9 and 11 for x8; or 9, 11, and 12 for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being ac- cessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data in- puts will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. except in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. other- wise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is auto- matically performed upon completion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. this device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is initi- ated at the earliest valid stage within a burst. this ?earliest valid stage? is determined as if an explicit precharge command was issued at the earliest pos- sible time, without violating t ras (min), as described for each burst type in the operation section of this data sheet. the user must not issue another command to the same bank until the precharge time ( t rp) is completed.
15 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance burst terminate the burst terminate command is used to trun- cate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated, as shown in the operation section of this data sheet. the open page which the read burst was terminated from remains open. auto refresh auto refresh is used during normal operation of the ddr sdram and is analogous to cas#-before- ras# (cbr) refresh in fpm/edo drams. this com- mand is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an auto refresh command. the 512mb ddr sdram requires auto refresh cycles at an average interval of 7.8125s (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the abso- lute refresh interval is provided. a maximum of eight auto refresh command can be posted to any given ddr sdram, meaning that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 7.8125s (70.3s). this maximum absolute interval is to allow future support for dll updates internal to the ddr sdram to be restricted to auto refresh cycles, with- out allowing excessive drift in t ac between updates. although not a jedec requirement, to provide for future functionality features, cke must be active (high) during the auto refresh period. the auto refresh period begins when the auto refresh command is registered and ends t rfc lat er. self refresh the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). the dll is automatically disabled upon entering self re- fresh and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). input signals except cke are ?don?t care? during self refresh. the procedure for exiting self refresh requires a se- quence of commands. first, ck must be stable prior to cke going back high. once cke is high, the ddr sdram must have nop commands issued for t xsnr because time is required for the completion of any in- ternal refresh in progress. a simple algorithm for meet- ing both refresh and dll requirements is to apply nops for 200 clock cycles before applying any other com- mand.
16 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance operations bank/row activation before any read or write commands can be is- sued to a bank within the ddr sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated, as shown in figure 4. after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specifi- cation of 20ns with a 133 mhz clock (7.5ns period) re- sults in 2.7 clocks rounded to 3. this is reflected in figure 5, which covers any case where 2 < t rcd (min)/ t ck 3. (figure 5 also shows the same case for t rcd; the same procedure is used to convert other specification limits from time units to clock cycles). a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the mini- mum time interval between successive active com- mands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access over- head. the minimum time interval between successive active commands to different banks is defined by t rrd. figure 5 example: meeting t rcd ( t rrd) min when 2 < t rcd ( t rrd) min/ t ck 3 figure 4 activating a specific row in a specific bank cs# we# cas# ras# cke a0-a12 ra ra = row address ba = bank address high ba0,1 ba ck ck# t command ba0, ba1 act act nop rrd t rcd ck ck# bank x bank y a0-a12 row row nop rd/wr nop bank y col nop t0 t1 t2 t3 t4 t5 t6 t7 don ? t care nop
17 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance reads read bursts are initiated with a read command, as shown in figure 6. the starting column and bank addresses are pro- vided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the ge- neric read commands used in the following illustra- tions, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available fol- lowing the cas latency after the read command. each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of ck and ck#). figure 7 shows general timing for each possible cas latency setting. dqs is driven by the ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data- out element is known as the read postamble. upon completion of a burst, assuming no other com- mands have been initiated, the dqs will go high-z. a detailed explanation of t dqsq (valid data- out skew), t qh (data-out window hold), the valid data window are depicted in figure 27. a detailed explana- tion of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) is depicted in figure 28. data from any read burst may be concatenated with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued x cycles after the first read com- mand, where x equals the number of desired data ele- ment pairs (pairs are required by the 2 n -prefetch ar- chitecture). this is shown in figure 8. a read com- mand can be initiated on any clock cycle following a previous read command. nonconsecutive read data is shown for illustration in figure 9. full-speed random read accesses within a page (or pages) can be performed as shown in figure 10. figure 6 read command cs# we# cas# ras# cke ca x4: a0-a9, a11, a12 x8: a0-a9, a11 x16: a0-a9 a10 ba0,1 high en ap dis ap ba x8: a12 x16: a11, a12 ck ck# ca = column address ba = bank address en ap = enable auto precharge dis ap = disable auto precharge don ? t care
18 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 7 read burst ck ck# command read nop nop nop nop nop address bank a, col n read nop nop nop nop nop bank a , col n cl = 2 note : 1. do n = data-out from column n . 2. burst length = 4. 3. three subsequent elements of data-out appear in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. ck ck# command address dq dqs cl = 2.5 dq dqs do n do n t0 t1 t2 t3 t2n t3n t4 t5 t0 t1 t2 t3 t2n t3n t4 t5 don ? t care transitioning data
19 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 8 consecutive read bursts ck ck# command read nop read nop nop nop address bank, col n bank, col b command read nop read nop nop nop address bank, col n bank, col b cl = 2 ck ck# command address dq dqs cl = 2.5 dq dqs do n do b do n do b t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n note : 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first). 3. three subsequent elements of data-out appear in the programmed order following do n. 4. three (or seven) subsequent elements of data-out appear in the programmed order following do b. 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies only when read commands are issued to same device. don ? t care transitioning data
20 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 9 nonconsecutive read bursts ck ck# command read nop nop nop nop nop address bank, col n read bank, col b command address cl = 2 ck ck# command address dq dqs cl = 2.5 dq dqs do n t0 t1 t2 t3 t2n t3n t4 t5 t5n t6 note : 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first). 3. three subsequent elements of data-out appear in the programmed order following do n. 4. three (or seven) subsequent elements of data-out appear in the programmed order following do b. 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies when read commands are issued to different devices or nonconsecutive reads. read nop nop nop nop nop bank, col n read bank, col b t0 t1 t2 t3 t2n t3n t4 t5 t5n t6 do b do n do b don ? t care transitioning data
21 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 10 random read accesses ck ck# command read read read nop nop address bank, col n bank, col x bank, col b bank, col x bank, col b read bank, col g command address cl = 2 ck ck# command address dq dqs cl = 2.5 dq dqs do n do x' do g do n' do b do x do b' do n do x' do n' do b do x do b' t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n note : 1. do n (or x or b or g ) = data-out from column n (or column x or column b or column g ). 2. burst length = 2 or 4 or 8 (if 4 or 8, the following burst interrupts the previous). 3. n ' or x ' or b ' or g ' indicates the next data-out following do n or do x or do b or do g , respectively . 4. reads are to an active row in any bank . 5. shown with nominal t ac, t dqsck, and t dqsq. read read read nop nop bank, col n read bank, col g t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n don ? t care transitioning data
22 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance data from any read burst may be truncated with a burst terminate command, as shown in figure 11. the burst terminate latency is equal to the read (cas) latency, i.e., the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architec- ture). data from any read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst ter- minate command must be used, as shown in figure 12. the t dqss (min) case is shown; the t dqss (max) case has a longer bus idle time. ( t dqss [min] and t dqss [max] are defined in the section on writes.) a read burst may be followed by, or truncated with, a precharge command to the same bank provided that auto precharge was not activated. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). this is shown in figure 13. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hid- den during the access of the last data elements. reads (continued)
23 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 11 terminating a read burst ck ck# command read bst 5 nop nop nop nop address bank a , col n read bst 5 nop nop nop nop bank a , col n cl = 2 note : 1. do n = data-out from column n . 2. burst length = 4. 3. subsequent element of data-out appears in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. 5. bst = burst terminate command, page remains open. ck ck# command address dq dqs cl = 2.5 dq dqs do n do n t0 t1 t2 t3 t2n t4 t5 t0 t1 t2 t3 t2n t4 t5 don ? t care transitioning data
24 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 12 read to write ck ck# command read bst 7 nop nop nop address bank, col n write bank, col b t0 t1 t2 t3 t2n t4 t5 t4n t5n note : 1. do n = data-out from column n . 2. di b = data-in from column b . 3. burst length = 4 in the cases shown (applies for bursts of 8 as well; if the burst length is 2, the bst command shown can be nop). 4. one subsequent element of data-out appears in the programmed order following do n. 5. data-in elements are applied following di b in the programmed order . 6. shown with nominal t ac, t dqsck, and t dqsq. 7. bst = burst terminate command, page remains open. cl = 2 dq dqs dm t (min) dqss di b ck ck# command read bst 7 nop write nop address bank a , col n nop t0 t1 t2 t3 t2n t4 t5 t5n cl = 2.5 dq dqs do n dm t (min) dqss di b don ? t care transitioning data do n
25 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 13 read to precharge ck ck# command 6 read nop pre nop nop act address bank a , col n bank a , ( a or all ) bank a , row read nop pre nop nop act bank a , col n cl = 2 t rp t rp note : 1. do n = data-out from column n . 2. burst length = 4, or an interrupted burst of 8. 3. three subsequent elements of data-out appear in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. 5. read to precharge equals two clocks, which allows two data pairs of data-out. 6. a read command with auto-precharge enabled would cause a precharge to be performed at x number of clock cycles after the read command, where x = bl / 2. 7. pre = precharge command; act = active command. ck ck# command 6 address dq dqs cl = 2.5 dq dqs do n do n t0 t1 t2 t3 t2n t3n t4 t5 t0 t1 t2 t3 t2n t3n t4 t5 bank a , ( a or all ) bank a , row don ? t care transitioning data
26 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance writes write bursts are initiated with a write command, as shown in figure 14. the starting column and bank addresses are pro- vided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the ge- neric write commands used in the following illustra- tions, auto precharge is disabled. during write bursts, the first valid data-in ele- ment will be registered on the first rising edge of dqs following the write command, and subsequent data elements will be registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in ele- ment is known as the write postamble. the time between the write command and the first corresponding rising edge of dqs ( t dqss) is speci- fied with a relatively wide range (from 75 percent to 125 percent of one clock cycle). all of the write diagrams show the nominal case, and where the two extreme cases (i.e., t dqss [min] and t dqss [max]) might not be intuitive, they have also been included. figure 15 shows the nominal case and the extremes of t dqss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dqs will re- main high-z and any additional input data will be ig- nored. data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any positive edge of clock following the previous write command. the first data element from the new burst is applied after either the last element of a com- pleted burst or the last desired data element of a longer burst which is being truncated. the new write com- mand should be issued x cycles after the first write command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). figure 16 shows concatenated bursts of 4. an ex- ample of nonconsecutive writes is shown in figure 17. full-speed random write accesses within a page or pages can be performed as shown in figure 18. data for any write burst may be followed by a subsequent read command. to follow a write with- out truncating the write burst, t wtr should be met as shown in figure 19. data for any write burst may be truncated by a subsequent read command, as shown in figure 20. note that only the data-in pairs that are registered figure 14 write command prior to the t wtr period are written to the internal ar- ray, and any subsequent data-in should be masked with dm as shown in figure 21. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met as shown in figure 22. data for any write burst may be truncated by a subsequent precharge command, as shown in fig- ures 23 and 24. note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data-in should be masked with dm as shown in figures 23 and 24. after the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. cs# we# cas# ras# cke ca a10 ba0,1 high en ap dis ap ba ck ck# ca = column address ba = bank address en ap = enable auto precharge dis ap = disable auto precharg e don ? t care x4: a0 ? a9, a11, a12 x8: a0-a9, a11 x16: a0 ? a9 x8: a12 x16:a11, a12
27 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 15 write burst dqs note: 1. di b = data-in for column b . 2. three subsequent elements of data-in are applied in the programmed order following di b . 3. an uninterrupted burst of 4 is shown. 4. a10 is low with the write command (auto precharge is disabled). t dqss (max) t dqss (nom) t dqss (min) t dqss dm dq ck ck# command write nop nop address bank a , col b nop t0 t1 t2 t3 t2n dqs t dqss dm dq dqs t dqss dm dq di b di b di b don ? t care transitioning data
28 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 16 consecutive write to write ck ck# command write nop write nop nop address bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n note : 1. di b , etc. = data-in for column b , etc. 2. three subsequent elements of data-in are applied in the programmed order following di b . 3. three subsequent elements of data-in are applied in the programmed order following di n . 4. an uninterrupted burst of 4 is shown . 5. each write command may be to any bank. t3n t1n dq dqs dm di n di b don ? t care transitioning data t dqss t dqss (nom)
29 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 17 nonconsecutive write to write ck ck# command write nop nop nop nop address bank, col b write bank, col n t0 t1 t2 t3 t2n t4 t5 t4n note : 1. di b , etc. = data-in for column b , etc. 2. three subsequent elements of data-in are applied in the programmed order following di b . 3. three subsequent elements of data-in are applied in the programmed order following di n . 4. an uninterrupted burst of 4 is shown . 5. each write command may be to any bank. t1n t5n dq dqs dm di n di b t dqss (nom) t dqss don ? t care transitioning data
30 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 18 random write cycles t dqss (nom) ck ck# command write write write write nop address bank, col b bank, col x bank, col n bank, col g write bank, col a t0 t1 t2 t3 t2n t4 t5 t4n note : 1. di b , etc. = data-in for column b , etc. 2. b' , etc. = the next data-in following di b , etc., according to the programmed burst order. 3. programmed burst length = 2, 4, or 8 in cases shown. 4. each write command may be to any bank. t1n t3n t5n dq dqs dm di b di b' di x di x' di n di n' di a di a' di g di g' don ? t care transitioning data
31 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 19 write to read ? uninterrupting t dqss (nom) ck ck# command write nop nop read nop nop address bank a , col b bank a , col n nop t0 t1 t2 t3 t2n t4 t5 note : 1. di b = data-in for column b . 2. three subsequent elements of data-in are applied in the programmed order following di b . 3. an uninterrupted burst of 4 is shown. 4. t wtr is referenced from the first positive ck edge after the last data-in pair. 5. the read and write commands are to same device. however, the read and write commands may be to different devices, in which case t wtr is not required and the read command could be applied earlier. 6. a10 is low with the write command (auto precharge is disabled). t1n t6 t6n t wtr cl = 2 dq dqs dm di b di n t dqss t dqss (min) cl = 2 dq dqs dm di b di n t dqss t dqss (max) cl = 2 dq dqs dm di b di n t dqss don ? t care transitioning data
32 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 20 write to read ? interrupting t dqss (nom) ck ck# command write nop nop nop nop nop address bank a , col b bank a , col n read t0 t1 t2 t3 t2n t4 t5 t5n note : 1. di b = data-in for column b . 2. an interrupted burst of 4 or 8 is shown; two data elements are written. 3. one subsequent element of data-in is applied in the programmed order following di b . 4. t wtr is referenced from the first positive ck edge after the last data-in pair. 5. a10 is low with the write command (auto precharge is disabled). 6. dqs is required at t2 and t2n (nominal case) to register dm. 7. if the burst of 8 was used, dm would not be required at t3 -t4n because the read command would mask the last two data elements. t1n t6 t6n t wtr cl = 2 dq dqs dm di b di n t dqss (min) cl = 2 dq dqs dm di b t dqss (max) cl = 2 dq dqs dm di b di n di n don ? t care transitioning data t dqss t dqss t dqss
33 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 21 write to read ? odd number of data, interrupting t dqss (nom) ck ck# command write nop nop nop nop nop address bank a , col b bank a , col n read t0 t1 t2 t3 t2n t4 t5 note : 1. di b = data-in for column b . 2. an interrupted burst of 4 is shown; one data element is written. 3. t wtr is referenced from the first positive ck edge after the last desired data-in pair (not the last two data elements). 4. a10 is low with the write command (auto precharge is disabled). 5. dqs is required at t1n, t2, and t2n (nominal case) to register dm. 6. if the burst of 8 was used, dm would not be required at t3 -t4n because the read command would mask the last four data elements. t1n t6 t6n t5n t wtr cl = 2 dq dqs dm di b di n t dqss (min) cl = 2 dq dqs dm di b di n t dqss (max) cl = 2 dq dqs dm di b di n don ? t care transitioning data t dqss t dqss t dqss
34 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 22 write to precharge ? uninterrupting t dqss (nom) ck ck# command write nop nop nop pre 7 nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 note : 1. di b = data-in for column b . 2. three subsequent elements of data-in are applied in the programmed order following di b . 3. an uninterrupted burst of 4 is shown. 4. t wr is referenced from the first positive ck edge after the last data-in pair. 5. the precharge and write commands are to the same device. however, the precharge and write commands may be to different devices, in which case t wr is not required and the precharge command could be applied earlier. 6. a10 is low with the write command (auto precharge is disabled). 7. pre = precharge command. t1n t6 t wr t rp dq dqs dm di b t dqss (min) dq dqs dm di b t dqss (max) dq dqs dm di b don ? t care transitioning data t dqss t dqss t dqss
35 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 23 write to precharge ? interrupting t dqss t dqss (nom) ck ck# command write nop nop pre 9 nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 note : 1. di b = data-in for column b . 2. subsequent element of data-in is applied in the programmed order following di b . 3. an interrupted burst of 4 is shown; two data elements are written. 4. t wr is referenced from the first positive ck edge after the last data-in pair. 5. the precharge and write commands are to the same bank. 6. a10 is low with the write command (auto precharge is disabled). 7. dqs is required at t2 and t2n (nominal case) to register dm. 8. if the burst of 8 was used, dm would be required at t3 and t3n and not at t4 and t4n because the precharge command would mask the last two data elements. 9. pre = precharge command. t1n t6 t wr t rp dq dqs dm di b t dqss t dqss (min) dq dqs dm di b t dqss t dqss (max) dq dqs dm di b don ? t care transitioning data
36 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 24 write to precharge odd number of data, interrupting t dqss t dqss (nom) ck ck# command write nop nop pre 9 nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 note : 1. di b = data-in for column b . 2. subsequent element of data-in is applied in the programmed order following di b . 3. an interrupted burst of 4 is shown; one data element is written. 4. t wr is referenced from the first positive ck edge after the last data-in pair. 5. the precharge and write commands are to the same bank. 6. a10 is low with the write command (auto precharge is disabled). 7. dqs is required at t1n, t2 and t2n (nominal case) to register dm. 8. if the burst of 8 was used, dm would be required at t3 and t3n and not at t4 and t4n because the precharge command would mask the last two data elements. 9. pre = precharge command. t1n t6 t wr t rp dq dqs dm di b t dqss t dqss (min) dq dqs dm t dqss t dqss (max) dq dqs dm di b di b don ? t care transitioning data
37 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 25 precharge command precharge the precharge command (figure 25) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) af- ter the precharge command is issued. input a10 t is t is no read/write access in progress exit power-down mode enter power-down mode cke ck ck# command nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop valid t0 t1 t2 ta0 ta1 ta2 valid don ? t care determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. power-down (cke not active) unlike sdr sdrams, ddr sdrams require cke to be active at all times an access is in progress: from the issuing of a read or write command until comple- tion of the burst. thus a clock suspend is not supported. for reads, a burst completion is defined when the read postamble is satisfied; for writes, a burst completion is defined when the write postamble is satisfied. power-down (figure 26) is entered when cke is reg- istered low. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding ck, ck#, and cke. for maximum power savings, the dll is frozen during precharge power-down. exiting power-down requires the device to be at the same voltage and frequency as when it entered power-down. however, power-down duration is limited by the refresh requirements of the device ( t refc). while in power-down, cke low and a stable clock signal must be maintained at the inputs of the ddr sdram, while all other input signals are ?don?t care.? the power-down state is synchronously exited when cke is registered high (in conjunction with a nop or deselect command). a valid executable command may be applied one clock cycle later. figure 26 power-down cs# we# cas# ras# cke a10 ba0,1 high all banks one bank ba a0 ? a9, a11, a12 ck ck# ba = bank address (if a10 is low; otherwise ? don ? t care ? ) don ? t care
38 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance truth table 2 ? cke (notes: 1-4) cke n-1 cke n current state command n action n notes l l power-down x m aintain power-down self refresh x maintain self refresh l h power-down deselect or nop exit power-down self refresh deselect or nop exit self refresh 5 h l all banks idle deselect or nop precharge power-down entry bank(s) active deselect or nop active power-down entry all banks idle auto refresh self refresh entry h h see truth table 3 note: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. deselect or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of 200 clock cycles is needed before applying a read command for the dll to lock.
39 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance truth table 3 ? current state bank n - command to bank n (notes: 1-6; notes appear below and on next page) current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/continue previous operation) l l h h active (select and activate row) idle l l l h auto refresh 7 llll load mode register 7 l h l h read (select column and start read burst) 10 row active l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read l h l h read (select column and start new read burst) 10 (auto- l h l l write (select col umn and start write burst) 10, 12 precharge l l h l precharge (truncate read burst, start precharge) 8 disabled) l h h l burst terminate 9 write l h l h read (select column and start read burst) 10, 11 (auto- l h l l write (select column and start new write burst) 10 precharge l l h l precharge (truncate write burst, start precharge) 8, 11 disabled) note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted (i.e., the current state is for a specific bank and the com- mands shown are those allowed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions: idle: the b ank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occur- ring during these states. allowable commands to the other bank are determined by its current state and truth table 3, and according to truth table 4. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the ? row active ? state. read w/auto- precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto- precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state.
40 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance note (continued): 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the ddr sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the ddr sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle, and bursts are not in progress. 8. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking. 12. a write command may be applied after the completion of the read burst; otherwise, a burst termi- nate must be used to end the read burst prior to asserting a write command.
41 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance truth table 4 ? current state bank n - command to bank m (notes: 1-6; notes appear below and on next page) current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle xxxx any command otherwise allowed to bank m row l l h h active (select and activate row) activating, l h l h read (select column and start read burst) 7 active, or l h l l write (select column and start write burst) 7 precharging l l h l precharge read l l h h active (select and activate row) (auto- l h l h read (select column and start new read burst) 7 precharge l h l l write (select col umn and start write burst) 7, 9 disabled) l l h l precharge write l l h h active (select and activate row) (auto- l h l h read (select column and start read burst) 7, 8 precharge l h l l w rite (select column and start new write burst) 7 disabled) l l h l precharge read l l h h active (select and activate row) (with auto- l h l h read (select column and start new read burst) 7, 3a precharge) l h l l write (select col umn and start write burst) 7, 9, 3a l l h l precharge write l l h h active (select and activate row) (with auto- l h l h read (select column and start read burst) 7, 3a precharge) l h l l write (select column and start new write burst) 7, 3a l l h l precharge note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsnr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. (notes continued on next page)
42 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance from command to command mini mum delay (with concurrent auto precharge) write w/ap read or read w/ap [1 + (bl/2)] t ck + t wtr write or write w/ap (bl/2) tck precharge 1 t ck active 1 t ck read w/ap read or read w/ap (bl/2) * t ck write or write w/ap [cl ru + (bl/2)] t ck precharge 1 t ck active 1 t ck note (continued): 3.current state definitions: idle: the b ank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see following text ? 3a write with auto precharge enabled: see following text ? 3a 3a. the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge com- mand that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when t wr ends,with t wr measured as if auto precharge was disabled. the access period starts with registration of the command and ends where the precharge period (or t rp) begins. this device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. in either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). 3b. the minimum delay from a read or write command with auto precharge enabled, to a command to a different bank is summarized below. cl ru = cas latency (cl) rounded up to the next integer bl = bust length 4. auto refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of the read burst; otherwise, a burst termi- nate must be used to end the read burst prior to asserting a write command.
43 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance absolute maximum ratings* v dd supply voltage relative to v ss ............. -1v to + 3.6v v dd q supply voltage relative to v ss .......... -1v to + 3.6v v ref and inputs voltage relative to v ss ........ -1v to + 3.6v i/o pins voltage relative to v ss ........ -0.5v to v dd q +0.5v operating temperature, t a (ambient) .... 0c to +70c storage temperature (plastic) ............ -55c to +150c power dissipation ........................................................ 1w short circuit output current ................................. 50ma *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1 ? 5, 16; notes appear on pages 50 ? 53) (0 c t a +70 c; v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v) parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v 36, 41 i/o supply voltage v dd q 2.3 2.7 v 36, 41, 44 i/o reference voltage v ref 0.49 x v dd q 0.51 x v dd q v 6, 44 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 7, 44 input high (logic 1) voltage v ih ( dc )v ref + 0.15 v dd + 0.3 v 28 input low (logic 0) voltage v il ( dc ) -0.3 v ref - 0.15 v 28 input leakage current any input 0v v in v dd , v ref pin 0v v in 1.35v i i -2 2 a (all other pins not under test = 0v) output leakage current i oz -5 5 a (dqs are disabled; 0v v out v dd q) output levels: full drive option - x4, x8, x16 high current (v out = v dd q-0.373v, minimum v ref , minimum v tt )i oh -16.8 ? ma 37, 39 low current (v out = 0.373v, maximum v ref , maximum v tt )i ol 16.8 ? ma output levels: reduced drive option - x16 only high current (v out = v dd q-0.763v, minimum v ref , minimum v tt )i ohr -9 ? ma 38, 39 low current (v out = 0.763v, maximum v ref , maximum v tt )i olr 9 ? ma ac input operating conditions (notes: 1 ? 5, 14, 16; notes appear on pages 50 ? 53) (0 c t a +70 c; v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v) parameter/condition symbol min max units notes input high (logic 1) voltage v ih ( ac )v ref + 0.310 ? v 14, 28, 40 input low (logic 0) voltage v il ( ac ) ? v ref - 0.310 v 14, 28, 40 i/o reference voltage v ref ( ac ) 0.49 x v dd q 0.51 x v dd qv 6
44 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 27 input voltage waveform 0.940v 1.100v 1.200v 1.225v 1.250v 1.275v 1.300v 1.400v 1.560v v il ac v il dc v ref -ac noise v ref -dc error v ref +dc error v ref +ac noise v ih dc v ih ac v oh(min) (1.670v 1 for sstl2 termination) v in ac - provides margin between v ol (max) and v il ac v ss q v dd q (2.3v minimum) v ol (max) (0.83v 2 for sstl2 termination) system noise margin (power/ground, crosstalk, signal integrity attenuation) note: 1. v oh (min) with test load is 1.927v 2. v ol (max) with test load is 0.373v 3. numbers in diagram reflect nomimal values utilizing circuit below. reference point 25 ? 25 ? v tt transmitter receiver
45 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance clock input operating conditions (notes: 1 ? 5, 15, 16, 30; notes appear on pages 50 ? 53) (0 c t a + 70 c; v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v) parameter/condition symbol min max units notes clock input mid-point voltage; ck and ck# v mp ( dc ) 1.15 1.35 v 6, 9 clock input voltage level; ck and ck# v in ( dc ) -0.3 v dd q + 0.3 v 6 clock input differential voltage; ck and ck# v id ( dc ) 0.36 v dd q + 0.6 v 6, 8 clock input differential voltage; ck and ck# v id ( ac ) 0.7 v dd q + 0.6 v 8 clock input crossing point voltage; ck and ck# v ix ( ac ) 0.5 x v dd q - 0.2 0.5 x v dd q + 0.2 v 9 figure 28 ? sstl_2 clock input ck# ck 2.80v 2 3 5 5 maximum clock level minimum clock level 4 - 0.30v 1.25v 1.45v 1.05v v id (ac) v id (dc) x 1 v mp (dc) v ix (ac) note: 1. this provides a minimum of 1.15v to a maximum of 1.35v, and is always half of v dd q. 2. ck and ck# must cross in this region. 3. ck and ck# must meet at least v id (dc) min when static and is centered around v mp (dc) 4. ck and ck# must have a minimum 700mv peak to peak swing. 5. ck or ck# may not be more positive than v dd q + 0.3v or more negative than vss - 0.3v. 6. for ac operation, all dc clock requirements must also be satisfied. 7. numbers in diagram reflect nominal values. x
46 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance capacitance (x4, x8) (note: 13; notes appear on pages 50 ? 53) parameter symbol min max units notes delta input/output capacitance: dqs, dqs, dm dc io ? 0.50 pf 24 delta input capacitance: command and address dc i 1 ? 0.50 pf 29 delta input capacitance: ck, ck# dc i 2 ? 0.25 pf 29 input/output capacitance: dqs, dqs, dm c io 4.0 5.0 pf input capacitance: command and address c i 1 2.0 3.0 pf input capacitance: ck, ck# c i 2 2.0 3.0 pf input capacitance: cke c i 3 2.0 3.0 p f i dd specifications and conditions (x4, x8) (notes: 1 ? 5, 10, 12, 14; notes appear on pages 50 ? 53) (0 c t a +70 c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v) parameter/condition symbol -75/-75z -8 units notes operating current: one bank; active-precharge; t rc = t rc(min); i dd 0 tbd tbd ma 22, 48 t ck = t ck(min); dq, dm, and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles operating current: one bank; active-read-precharge; burst = 2; i dd 1 tbd tbd ma 22, 48 t rc = t rc(min); t ck = t ck(min); i out = 0ma; address and control inputs changing once per clock cycle precharge power-down standby current: all banks idle; i dd 2p 3 3 ma 23, 32 power-down mode; t ck = t ck(min); cke = low; 50 idle standby current: cs# = high; all banks idle; t ck = t ck(min); i dd 2f 35 30 ma 51 cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm active power-down standby current: one bank active; i dd 3p 3 3 ma 23, 32 power-down mode; t ck = t ck(min); cke = low 50 active standby current: cs# = high; cke = high;one bank; i dd 3n 35 30 ma 22 active-precharge; t rc = t ras(max); t ck = t ck(min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle operating current: burst = 2; reads; continuous burst; one bank i dd 4r tbd tbd ma 22, 48 active; address and control inputs changing once per clock cycle; t ck = t ck(min); i out = 0ma operating current: burst = 2; writes; continuous burst; one bank i dd 4w tbd tbd ma 22 active; address and control inputs changing once per clock cycle; t ck = t ck(min); dq, dm, and dqs inputs changing twice per clock cycle auto refresh current t rc = 7.8125s i dd 5 6 6 ma 27,50 t rc = t rc(min) i dd 6 tbd tbd ma 22,50 self refresh current: cke 0.2v standard i dd 7 tbd tbd ma 11 low power (l) i dd 7 tbd tbd ma 11 operating current: four bank interleaving reads (bl=4) with auto i dd 8 tbd tbd ma 22, 49 precharge, t rc = t rc (min) ; t ck = t rc (min) ; address and control inputs change only during active read, or write commands. max
47 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance capacitance (x16) (note: 13; notes appear on pages 50 ? 53) parameter symbol min max units notes delta input/output capacitance: dq0-dq7, ldqs, ldm dc iol ? 0.50 pf 24 delta input/output capacitance: dq8-dq15, udqs, udm dc iou ? 0.50 pf 24 delta input capacitance: command and address dc i 1 ? 0.50 pf 29 delta input capacitance: ck, ck# dc i 2 ? 0.25 pf 29 input/output capacitance: dqs, ldqs, udqs, ldm, udm c io 4.0 5.0 pf input capacitance: command and address c i 1 2.0 3.0 pf input capacitance: ck, ck# c i 2 2.0 3.0 pf input capacitance: cke c i 3 2.0 3.0 pf i dd specifications and conditions (x16) (notes: 1 ? 5, 10, 12, 14; notes appear on pages 50 ? 53) (0 c t a +70 c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v) parameter/condition symbol -75/-75z -8 units notes operating current: one bank; active-precharge; t rc = t rc (min) ; i dd 0 tbd tbd ma 22, 48 t ck = t ck (min) ; dq, dm, and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles; operating current: one bank; active-read-precharge; burst = 2; i dd 1 tbd tbd ma 22, 48 t rc = t rc(min); t ck = t ck(min); i out = 0ma; address and control inputs changing once per clock cycle precharge power-down standby current: all banks idle; i dd 2p 3 3 ma 23, 32 power-down mode; t ck = t ck(min); cke = low; 50 idle standby current: cs# = high; all banks idle; t ck = t ck (min) ; i dd 2f 40 35 ma 51 cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm active power-down standby current: one bank active; i dd 3p 3 3 ma 23, 32 power-down mode; t ck = t ck(min); cke = low 50 active standby current: cs# = high; cke = high; one bank; i dd 3n 35 30 ma 22 active-precharge; t rc = t ras(max); t ck = t ck(min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle operating current: burst = 2; reads; continuous burst; one bank i dd 4r tbd tbd ma 22, 48 active; address and control inputs changing once per clock cycle; t ck = t ck(min); i out = 0ma operating current: burst = 2; writes; continuous burst; one bank i dd 4w tbd tbd ma 22 active; address and control inputs changing once per clock cycle; t ck = t ck(min); dq, dm, and dqs inputs changing twice per clock cycle auto refresh current t rc = 7.8125s i dd 5 6 6 ma 27,50 t rc = 7.8125s i dd 5 6 6 ma 27,50 self refresh current: cke 0.2v standard i dd 6 tbd tbd ma 11 low power (l) i dd 7 tbd tbd ma 11 operating current: four bank interleaving reads (bl=4) with i dd 7 tbd tbd ma 22, 49 auto precharge with , t rc = t rc (min) ; t ck = t rc (min) ; address and control inputs change only during active read, or write commands. max
48 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance electrical characteristics and recommended ac operating conditions (notes: 1 ? 5, 14 ? 17, 33; notes appear on pages 50 ? 53) (0 c t a +70 c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v) ac characteristics -75z -75 -8 parameter symbol min max min max min max units notes access window of dqs from ck/ck# t ac -0.75 + 0.75 -0.75 + 0.75 -0.8 +0.8 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 30 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 30 clock cycle time cl = 2.5 t ck (2.5) 7.5 13 7.5 13 8 13 ns 45, 52 cl = 2 t ck (2) 7.5 13 10 13 10 13 ns 45, 52 dq and dm input hold time relative to dqs t dh 0.5 0.5 0.6 ns 26, 31 dq and dm input setup time relative to dqs t ds 0.5 0.5 0.6 ns 26, 31 dq and dm input pulse width (for each input) t dipw 1.75 1.75 2 ns 31 access window of dqs from ck/ck# t dqsck -0.75 + 0.75 -0.8 + 0.75 -0.8 +0.8 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.5 0.5 0.6 ns 25, 26 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl t ch, t cl ns 34 data-out high-impedance window from ck/ck# t hz +0.75 +0.75 +0.8 ns 18,42 data-out low-impedance window from ck/ck# t lz -0.75 -0.75 -0.8 ns 18,43 address and control input hold time (fast slew rate) t ih f .90 .90 1.1 ns 14 address and control input setup time (fast slew rate) t is f .90 .90 1.1 ns 14 address and control input hold time (slow slew rate) t ih s 1 1 1.1 ns 14 address and control input setup time (slow slew rate) t ih s 1 1 1.1 ns 14 load mode register command cycle time t mrd 15 15 16 ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp t hp t hp ns 25, 26 - t qhs - t qhs - t qhs data hold skew factor t qhs 0.75 0.75 1 ns active to precharge command t ras 40 120,000 40 120,000 40 120,000 ns 35 active to read with auto precharge command t rap 20 20 20 ns 46 active to active/auto refresh command period t rc 65 65 70 ns auto refresh command period t rfc 75 75 80 ns 50 active to read or write delay t rcd 20 20 20 ns precharge command period t rp 20 20 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck 42 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 15 15 15 ns dqs write preamble t wpre 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 0 ns 20, 21 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 19 write recovery time t wr 15 15 15 ns internal write to read command delay t wtr 1 1 1 t ck data valid output window (dvw) na t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 25 refresh to refresh command interval t refc 70.3 70.3 70.3 s 23 average periodic refresh interval t refi 7.8 7.8 7.8 s 23 terminating voltage delay to v dd t vtd 0 0 0 ns exit self refresh to non-read command t xsnr 75 75 80 ns exit self refresh to read command t xsrd 200 200 200 t ck
49 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance slew rate derating values (note: 14; notes appear on pages 50 ? 53) (0 c t a +70 c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v) address / command speed slew rate t is t ih units -75z, -75 0.500v / ns 1 1 ns -75z, -75 0.400v / ns 1.05 1 ns -75z, -75 0.300v / ns 1.10 1 ns -75z, -75 0.200v / ns 1.15 1 ns -8 0.500v / ns 1.1 1.1 ns -8 0.400v / ns 1.15 1.1 ns -8 0.300v / ns 1.20 1.1 ns -8 0.200v / ns 1.25 1.1 ns slew rate derating values (note: 31; notes appear on pages 50 ? 53) (0 c t a +70 c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v) dq, dm, dqs speed slew rate t ds t dh units -75z, -75 0.500v / ns 0.50 0.50 ns -75z, -75 0.400v / ns 0.55 0.55 ns -75z, -75 0.300v / ns 0.60 0.60 ns -75z, -75 0.200v / ns 0.65 0.65 ns -8 0.500v / ns 0.60 0.60 ns -8 0.400v / ns 0.65 0.65 ns -8 0.300v / ns 0.70 0.70 ns -8 0.200v / ns 0.75 0.75 ns
50 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il ( ac ) and v ih ( ac ). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v dd q/2 of the transmit- ting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v dd q/2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref by-pass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 9. the value of v ix is expected to equal v dd q/2 of the transmitting device and must track variations in the dc level of the same. 10. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time at cl = 2 for -75z and -8, cl = 2.5 for -75 with the outputs open. 11. enables on-chip refresh and address counters. notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaran- teed for the full voltage range specified. 3. outputs measured with equivalent load: 12. i dd specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. this parameter is sampled. v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v, v ref = v ss , f = 100 mhz, t a = 25c, v out ( dc ) = v dd q/2, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 14. command/address input slew rate = 0.5v/ns. for -75 with slew rates 1v/ns and faster, t is and t ih are reduced to 900ps. if the slew rate is less than 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100mv/ns reduction in slew rate from the 500mv/ns. t ih has 0ps added, that is, it remains constant. if the slew rate exceeds 4.5v/ns, functionality is uncertain. 15. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 16. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.3 x v dd q is recognized as low. 17. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 18. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 19. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 22. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras( max ) for i dd measurements is the largest multiple of t ck that meets the maximum absolute value for t ras. 23. the refresh period 64ms. this equates to an output (v out ) reference point 50 ? v tt 30pf
51 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance average refresh rate of 7.8125s. however, an auto refresh command must be asserted at least once every 70.3s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 24. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 25. the valid data window is derived by achieving other specifications - t hp ( t ck/2), t dqsq, and t qh ( t hp - t qhs). the data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. the data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. referenced to each output group: x4 = dqs with dq0-dq3; x8 = dqs with dq0-dq7; x16 = ldqs with dq0-dq7; and udqs with dq8-dq15. 27. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else notes (continued) cke is low (i.e., during standby). 28. to maintain a valid level, the transitioning edge of the input must: a) sustain a constant slew rate from the current ac level through to the target ac level, v il ( ac ) or v ih ( ac ). b) reach at least the target ac level. c) after the ac target level is reached, continue to maintain at least the target dc level, v il ( dc ) or v ih ( dc ). 29. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. jedec specifies ck and ck# input slew rate must be 1v/ns (2v/ns if measured differentially). 31. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/ns, functionality is uncertain. 32. v dd must not vary more than 4% if cke is not active while any bank is active. derating data valid window ( t qh - t dqsq) 3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250 3.400 3.350 3.300 3.250 3.200 3.150 3.100 3.050 3.000 2.950 2.900 2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 clock duty cycle ns ?? -75 @ t ck = 10ns ?? -8 @ t ck = 10ns ?? -75 @ t ck = 7.5ns ?? -8 @ t ck = 8ns
52 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance notes (continued) 33. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 34. t hpmin is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck/ inputs, collectively during bank active. 35. reads and writes with autoprecharge are not allowed to be issued until t ras( min ) can be satisfied prior to the internal precharge com- mand being issued. 36. any positive glitch must be less than 1 / 3 of the clock cycle and not more than +400mv or 2.9 volts, whichever is less. any negative glitch must be less than 1 / 3 of the clock cycle and not exceed either -300mv or 2.2 volts, whichever is more positive. 37. normal output drive curves: a) the full variation in driver pull-down current from minimum to maximum process, tempera- ture and voltage will lie within the outer bounding lines of the v-i curve of figure a. b)the variation in driver pull-down current within nominal limits of voltage and tempera- ture is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure a. c) the full variation in driver pull-up current from minimum to maximum process, tempera- ture and voltage will lie within the outer bounding lines of the v-i curve of figure b. d)the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure b. e) the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0 volt, and at the same voltage and temperature. f) the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0 volt. 38.reduced output drive curves: a) the full variation in driver pull-down current from minimum to maximum process, tempera- ture and voltage will lie within the outer bounding lines of the v-i curve of figure c. b) the variation in driver pull-down current within nominal limits of voltage and tempera- ture is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure c. c) the full variation in driver pull-up current from minimum to maximum process, tempera- ture and voltage will lie within the outer bounding lines of the v-i curve of figure d. d) the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure d. e) the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4 for device drain-to-source voltages from 0.1v to 1.0 volt, and at the same voltage and temperature. f) the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1v to 1.0 volt. figure a pull-down characteristics 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 v out (v) i out (ma) figure b pull-up characteristics -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.00.51.01.52.02.5 v dd q - v out (v) i out (ma)
53 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance notes (continued) 39. the voltage levels used are derived from a minimum v dd level and the refernced test load. in practice, the voltage levels obtained from a properly terminated bus will provide signifi- cantly different voltage values. 40. v ih overshoot: v ih (max) = v dd q+1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. vil undershoot: vil(min) = -1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. v dd and v ddq must track each other. 42. this maximum value is derived from the referenced test load. in practice, the values obtained in a typical terminated design may reflect up to 310ps less for t hzmax and the last dvw. t hz(max) will prevail over t dqsck(max) + t rpst(max) condition. 43. for slew rates greater than 1v/ns the (lz) transition will start about 310ps earlier. t lz(min) will prevail over a t dqsck(min) + t rpre(max) condition. 4 4. during initialization, v ddq , v tt , and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd /v ddq are 0 volts, provided a minimum of 42 ohms of series resistance is used between the v tt supply and the input pin. figure c pull-down characteristics 0 10 20 30 40 50 60 70 80 0.0 0.5 1.0 1.5 2.0 2.5 v out (v) i out (ma) figure d pull-up characteristics -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0.0 0.2 0.4 0.6 0.8 1.0 v dd q - v out (v) i out (ma) 45. the current micron part operates below the slowest jedec operating frequency of 83 mhz. as such, future die may not reflect this option. 46. reserved for future use. 47. reserved for future use. 48. random addressing changing 50% of data changing at every transfer. 49. random addressing changing 100% of data changing at every transfer. 50. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t ref later. 51. idd2n specifies the dq, dqs, and dm to be driven to a valid high or low logic level. idd2q is similar to idd2f except idd2q specifies the address and control inputs to remain stable. although idd2f, idd2n, and idd2q are similar, idd2f is ?worst case.? 52. whenever the operating frequency is altered, not including jitter, the dll is required to be reset, and followed by 200 clock cycles.
54 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance note: the above characteristics are specified under best, worst, and nominal process variation/conditions. normal output drive characteristics pull-down current (ma) pull-up current (ma) voltage nominal nominal nominal nominal (v) low high minimum maximum low high minimum maximum 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.8 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2
55 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance note: the above characteristics are specified under best, worst, and nominal process variation/conditions. reduced output drive characteristics pull-down current (ma) pull-up current (ma) voltage nominal nominal nominal nominal (v) low high minimum maximum low high minimum maximum 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -7.8 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.9 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7
56 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 29 x4, x8 data output timing ? t dqsq, t qh and data valid window dq (last data valid) dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 dqs 1 dq (last data valid) dq (first data no longer valid) dq (first data no longer valid) all dqs and dqs, collectively 6 note: 1. dqs transitioning after dqs transition define t dqsq window. dqs transitions at t2 and at t2n are an ? early dqs, ? at t3 is a ? nominal dqs, ? and at t3n is a "late dqs" 2. for a x4, only two dqs apply. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid transition of dqs . 4. t qh is derived from t hp : t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 6. the data valid window is derived for each dqs transitions and is defined as t qh minus t dqsq. earliest signal transition latest signal transition t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 4 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 t hp 5 t hp 5 t hp 5 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 data valid window data valid window data valid window data valid window qfc#
57 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 29 a x16 data output timing ? t dqsq, t qh and data valid window dq (last data valid) 2 dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 ldqs 1 dq (last data valid) 2 dq (first data no longer valid) 2 dq (first data no longer valid) 2 dq0 - dq7 and ldqs, collectively 6 note: 1. dqs transitioning after dqs transition define t dqsq window. ldqs defines the lower byte and udqs defines the upper byte. 2. dq0, dq1, dq2, dq3, dq4, dq5, dq6, or dq7. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid transition of dqs . t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 data valid window data valid window dq (last data valid) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udqs 1 dq (last data valid) 7 dq (first data no longer valid) 7 dq (first data no longer valid) 7 dq8 - dq15 and udqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 4 t qh 4 t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 data valid window data valid window data valid window data valid window data valid window 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 6. the data valid window is derived for each dqs transition and is t qh minus t dqsq. 7. dq8, dq9, dq10, d11, dq12, dq13, dq14, or dq15. upper byte lower byte data valid window
58 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance figure 31 data input timing figure 30 data output timing - t ac and t dqsck ck ck# dqs, or ldqs/udqs 2 t0 7 t1 t2 t3 t4 t5 t2n t3n t4n t5n t6 note: 1. t dqsck is the dqs output window relative to ck and is the ? long term ? component of dqs skew. 2. dqs transitioning after dqs transition define t dqsq window. 3. all dqs must transition by t dqsq after dqs transitions, regardless of t ac. 4. t ac is the dq output window relative to ck, and is the ? long term ? component of dq skew. 5. t lz ( min) and t ac ( min) are the first valid signal transition. 6. t hz ( max ,and t ac ( max) are the latest valid signal transition. 7. read command with cl = 2 issued at t0. t rpst t lz (min) t dqsck 1 (max) t dqsck 1 (min) t dqsck 1 (max) t dqsck 1 (min) t hz (max) t rpre dq (last data valid) dq (first data valid) all dqs collectively 3 t ac 4 (min) t ac 4 (max) t lz (min) t hz (max) t2 t2 t2n t3n t4n t5n t2n t2n t3n t3n t4n t4n t5n t5n t3 t4 t4 t5 t5 t2 t3 t4 t5 t3 dqs t dqss t dqsh t wpst t dh t ds t dqsl t dss 2 t dsh 1 t dsh 1 t dss 2 dm dq ck ck# t0 3 t1 t1n t2 t2n t3 di b note: 1. t dsh ( min) generally occurs during t dqss ( min) . 2. t dss ( min) generally occurs during t dqss ( max) . 3. write command issued at t0. 4. for x16, ldqs controls the lower byte and udqs controls the upper byte. don ? t care transitioning data t wpre t wpres
59 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance initialize and load mode registers t vtd 1 cke lvcmos low level dq ba0, ba1 200 cycles of ck 3 load extended mode register load mode register 2 t mrd t mrd t rp t rfc t rfc 5 t is power-up: v dd and ck stable t = 200s high-z t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqs high-z a0-a9, a11, a12 ra a10 ra all banks ck ck# t ch t cl t ck v tt 1 v ref v dd v dd q command 6 lmr nop pre lmr ar ( ) ( ) ( ) ( ) ar act 5 t is t ih ba0 = h, ba1 = l t is t ih t is t ih ba0 = l, ba1 = l t is t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) code code t is t ih code code ( ) ( ) ( ) ( ) pre all banks t is t ih note: 1. v tt is not applied directly to the device; however, t vtd should be greater than or equal to zero to avoid device latch-up. v dd q , v dd q, v tt and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd /v dd q are 0 volts, provided a minimum of 42 ohms of series resistance is used between the v tt supply and the input pin. 2. although not required by the micron device, jedec specifies resetting the dll with a8 = h. 3. t mrd is required before any command can be applied, and 200 cycles of ck are required before a read command can be issued. 4. the two auto refresh commands at tc0 and td0 may be applied prior to the load mode register (lmr) command at ta0. 5. although not required by the micron device, jedec specifies issuing another lmr command (a8 = l) prior to activating any ban k. 6. pre = precharge command, lmr = load mode register command, ar = auto refresh command, act = active command, ra = row address, bank address ( ) ( ) ( ) ( ) t0 t1 t2 ta0 tb0 tc0 td0 te0 ( ) ( ) ( ) ( ) ( ) ( ) don ? t care ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp -75z -75 -8 symbol min max min max min max units t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ck (2.5) 7.5 13 7.5 13 8 13 ns t c k ( 2 ) 7.5 13 10 13 10 13 n s t ih 1 1 1.1 ns -75z -75 -8 symbol min max min max min max units t is 1 1 1.1 ns t mrd 15 15 16 ns t r f c 75 75 80 n s t rp 20 20 20 n s t vtd 0 0 0 ns timing parameters
60 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance power-down mode ck ck# command valid 1 nop addr cke note : 1. if this command is a precharge (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. if this command is an active (or if at least one row is already active), then the power-down mode shown is active power-down. 2. no column accesses are allowed to be in progress at the time power-down is entered. dq dm dqs valid t ck t ch t cl t is t is t ih t is t is t ih t ih t is enter 2 power-down mode exit power-down mode t refc ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 ta0 ta1 ta2 t2 nop don ? t care ( ) ( ) ( ) ( ) valid valid -75z -75 -8 symbol min max min max min max units t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ck (2.5) 7.5 13 7.5 13 8 13 ns -75z -75 -8 symbol min max min max min max units t c k ( 2 ) 7.5 13 10 13 10 13 n s t ih 1 1 1.1 ns t is 1 1 1.1 ns timing parameters
61 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance auto refresh mode ck ck# command 1 nop 2 valid valid nop 2 nop 2 pre cke ra a0-a9, a11, a12 1 a10 1 ba0, ba1 1 bank(s) 3 ba note : 1. pre = precharge, act = active, ar = auto refresh, ra = row address, ba = bank address. 2. nop commands are shown for ease of illustration; other valid commands may be possible at these times. cke must be active during clock positive transitions. 3. ? don ? t care ? if a10 is high at this point; a10 must be high if more than one bank is active (i.e., must precharge all active banks). 4. dm, dq, and dqs signals are all ? don ? t care ? /high-z for operations shown. 5. the second auto refresh is not required and is only shown as an example of two back-to-back auto refresh commands. ar nop 2 ar 5 nop 2 act nop 2 one bank all banks t ck t ch t cl t is t is t ih t ih t is t ih ra ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq 4 dm 4 dqs 4 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rfc 5 t rp t rfc t0 t1 t2 t3 t4 ta0 tb0 ta1 tb1 tb2 don ? t care ( ) ( ) ( ) ( ) -75z -75 -8 symbol min max min max min max units t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ck (2.5) 7.5 13 7.5 13 8 13 ns t c k ( 2 ) 7.5 13 10 13 10 13 n s -75z -75 -8 symbol min max min max min max units t ih 1 1 1.1 ns t is 1 1 1.1 ns t r f c 75 75 80 n s t rp 20 20 20 n s timing parameters
62 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance self refresh mode ck 1 ck# command 4 nop ar addr cke 1 valid dq dm dqs valid nop note : 1. clock must be stable before exiting self refresh mode. that is, the clock must be cycling within specifications by ta0. 2. device must be in the all banks idle state prior to entering self refresh mode. 3. t xsnr is required before any non-read command can be applied, and t xsrd (200 cycles of ck) is required before a read command can be applied. 4. ar = auto refresh command. t rp 2 t ch t cl t ck t is t xsnr/ t xsrd 3 t is t ih t is t is t ih t ih t is enter self refresh mode exit self refresh mode ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 tb0 ta1 ( ) ( ) ( ) ( ) ( ) ( ) don ? t care ( ) ( ) ( ) ( ) ta0 1 -75z -75 -8 symbol min max min max min max units t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ck (2.5) 7.5 13 7.5 13 8 13 ns t c k ( 2 ) 7.5 13 10 13 10 13 n s t ih 1 1 1.1 ns -75z -75 -8 symbol min max min max min max units t is 1 1 1.1 ns t rp 20 20 20 n s t xsnr 75 75 80 ns t xsrd 200 200 200 t ck timing parameters
63 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance bank read ? without auto precharge ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras 7 t rc t rp cl = 2 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 t8 dq 1 dqs case 1: t ac ( min) and t dqsck ( min) case 2: t ac ( max) and t dqsck ( max) dq 1 dqs t rpre t rpre t rpst t rpst t dqsck ( min) t dqsck ( max) t lz ( min) t lz ( max) t ac ( min) t lz ( min) do n t hz ( max) t ac ( max) t lz ( max) do n nop 6 nop 6 command 5 3 act ra ra col n read 2 pre 7 bank x ra ra ra bank x bank x 4 act bank x nop 6 nop 6 nop 6 t hz ( min) note: 1. do n = data-out from column n ; subsequent elements are provided in the programmed order. 2. burst length = 4 in the case shown. 3. disable auto precharge. 4. ? don ? t care ? if a10 is high at t5. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustration; other commands may be valid at these times. 7. the precharge command can only be applied at t5 if t ras minimum is met. 8. refer to figure 27, 27a, and 28 for detailed dqs and dq timing. one bank all banks don ? t care transitioning data x4: a0-a9, a11, a12 x8: a0-a11 x16: a0-a9 x8: a12 x16: a11, a12
64 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance bank read ? with auto precharge ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih is ih ra t rc t rp cl = 2 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 t8 dq 1 dqs case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 1 dqs t rpre t rpre t rpst t rpst t dqsck (min) t dqsck (max) t ac (min) t lz (min) do n t hz (max) t ac (max) t lz (max) do n nop 5 nop 5 command 4 3 act ra ra col n read 2,6 nop 5 bank x ra ra ra bank x act bank x nop 5 nop 5 nop 5 t hz (min) note: 1. do n = data-out from column n; subsequent elements are provided in the programmed order. 2. burst length = 4 in the case shown. 3. enable auto precharge. 4. act = active, ra = row address, ba = bank address. 5. nop commands are shown for ease of illustration; other commands may be valid at these times. 6. the read command can only be applied at t3 if t rap is satisfied at t3 7. refer to figure 27, 27a, and 28 for detailed dqs and dq timing. don ? t care transitioning data x4: a0-a9, a11,a12 x8: a0-a9, a11 x16: a0-a9 x8: a12 x16: a11, a12 t ras t lz (min) t lz (max) t rcd, t rap 6
65 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance bank write ? without auto precharge ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n note: 1. di n = data-out from column n ; subsequent elements are provided in the programmed order. 2. burst length = 4 in the case shown. 3. disable auto precharge. 4. ? don ? t care ? if a10 is high at t8. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustration; other commands may be valid at these times. 7 . t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 8 . t dss is applicable during t dqss (max) and is referenced from ck t5 or t6. nop 6 nop 6 command 5 3 act ra ra col n write 2 nop 6 one bank all banks bank x pre bank x nop 6 nop 6 nop 6 t dqsl t dqsh t wpst bank x 4 dq 1 dqs dm di b t ds t dh don ? t care transitioning data t dqss (nom) t wpre t wpres x4: a0-a9, a11, a12 x8: a0-a9, a11 x16: a0-a9 x8: a12 x16: a11, a12 -75z -75 -8 symbol min max min max min max units t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ck (2.5) 7.5 13 7.5 13 8 12 ns t c k ( 2 ) 7.5 13 10 13 10 12 n s t dh 0.5 0.5 0.6 ns t ds 0.5 0.5 0.6 ns t dqsh 0.35 0.35 0.35 t ck t dqsl 0.35 0.35 0.35 t ck t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck t dss 0.2 0.2 0.2 t ck -75z -75 -8 symbol min max min max min max units t dsh 0.2 0.2 0.2 t ck t ih 1 1 1.1 ns t is 1 1 1.1 ns t ras 40 120,000 40 120,000 40 120,000 ns t r c d 20 20 20 n s t rp 20 20 20 n s t wpre 0.25 0.25 0.25 t ck t wpres 0 0 0 ns t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck t wr 15 15 15 n s timing parameters
66 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance bank write ? with auto precharge ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n note: 1. di n = data-out from column n ; subsequent elements are provided in the programmed order. 2. burst length = 4 in the case shown. 3. enable auto precharge. 4. act = active, ra = row address, ba = bank address. 5. nop commands are shown for ease of illustration; other commands may be valid at these times. 6 . t dsh is applicable during t dqss ( min) and is referenced from ck t4 or t5. 7 . t dss is applicable during t dqss (max) and is referenced from ck t5 or t6. nop 5 nop 5 command 4 3 act ra ra col n write 2 nop 5 bank x nop 5 bank x nop 5 nop 5 nop 5 t dqsl t dqsh t wpst dq 1 dqs dm di b t ds t dh t dqss (nom) don ? t care transitioning data t wpres t wpre x4: a0-a9, a11 x8: a0-a9 x16: a0-a8 x4: a12 x8: a11, a12 x16: a9, a11, a12 -75z -75 -8 symbol min max min max min max units t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ck (2.5) 7.5 13 7.5 13 8 13 ns t c k ( 2 ) 7.5 13 10 13 10 13 n s t dh 0.5 0.5 0.6 ns t ds 0.5 0.5 0.6 ns t dqsh 0.35 0.35 0.35 t ck t dqsl 0.35 0.35 0.35 t ck t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck t dss 0.2 0.2 0.2 t ck -75z -75 -8 symbol min max min max min max units t dsh 0.2 0.2 0.2 t ck t ih 1 1 1.1 ns t is 1 1 1.1 ns t ras 40 120,000 40 120,000 40 120,000 ns t r c d 20 20 20 n s t rp 20 20 20 n s t wpre 0.25 0.25 0.25 t ck t wpres 0 0 0 ns t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck t wr 15 15 15 n s timing parameters
67 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance write ? dm operation ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n note: 1. di n = data-out from column n ; subsequent elements are provided in the programmed order. 2. burst length = 4 in the case shown. 3. disable auto precharge. 4. ? don ? t care ? if a10 is high at t8. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustration; other commands may be valid at these times. 7 . t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 8 . t dss is applicable during t dqss (max) and is referenced from ck t5 or t6. nop 6 nop 6 command 5 3 act ra ra col n write 2 nop 6 one bank all banks bank x pre bank x nop 6 nop 6 nop 6 t dqsl t dqsh t wpst bank x 4 dq 1 dqs dm di b t ds t dh don ? t care transitioning data t dqss (nom) t wpres t wpre x4: a0-a9, a11 x8: a0-a9 x16: a0-a8 x4: a12 x8: a11, a12 x16: a9, a11, a12 -75z -75 -8 symbol min max min max min max units t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ck (2.5) 7.5 13 7.5 13 8 13 ns t c k ( 2 ) 7.5 13 10 13 10 13 n s t dh 0.5 0.5 0.6 ns t ds 0.5 0.5 0.6 ns t dqsh 0.35 0.35 0.35 t ck t dqsl 0.35 0.35 0.35 t ck t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck t dss 0.2 0.2 0.2 t ck -75z -75 -8 symbol min max min max min max units t dsh 0.2 0.2 0.2 t ck t ih 1 1 1.1 ns t is 1 1 1.1 ns t ras 40 120,000 40 120,000 40 120,000 ns t r c d 20 20 20 n s t rp 20 20 20 n s t wpre 0.25 0.25 0.25 t ck t wpres 0 0 0 ns t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck t wr 15 15 15 n s timing parameters
68 512mb: x4, x8, x16 ddr sdram micron technology, inc., reserves the right to change products or specifications without notice. 512mx4x8x16ddr_b.p65 ? rev. b; pub 4/01 ?2001, micron technology, inc. 512mb: x4, x8, x16 ddr sdram advance (tg) option 66-pin plastic tsop (400 mil) note: 1. all dimensions in millimeters max or typical here noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. see detail a 0.10 0.65 typ 0.71 10.16 0.08 0.15 0.50 0.10 pin #1 id detail a 22.22 0.08 0.32 .075 typ +0.03 -0.02 +0.10 -0.05 1.20 max 0.10 0.25 11.76 0.10 0.80 typ 0.10 (2x) gage plane 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark and the micron logo and m logo are trademarks of micron technology, inc.

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